In recent years remarkable progress has been made in semiconductor (particularly in microcomputers) technology. The individual function circuits incorporated into these semiconductor integrated circuits must provide high performance.
Phase synchronizing circuits (hereafter PLL {phase locked loop circuits}) are widely used in semiconductor integrated circuits as frequency multipliers. A semiconductor integrated circuit incorporating an internal PLL circuit can generate clocks at a frequency N number of times higher than the reference (basic) frequency.
The PLL circuit must output a stable clock pulse. However, a distortion in the clock waveform output from the PLL circuit has become a problem along with lower supply voltages in recent years. Namely, the PLL circuit generates an output clock by utilizing a voltage controlled oscillator (VCO). However the output clock waveform becomes distorted due to jitter or fluctuations in the VCO supply voltage. Distortion in the output clock waveform might cause faulty operation in other function circuits that operate based on the output clock.
JP-A No. H10 (1998)-124167 discloses technology for selectively outputting clocks from separate oscillator circuits. FIG. 11 shows the technology of JP-A No. H10 (1998)-124167. A multiplexer 84 as shown in FIG. 11, changes the output clock from the clock of the oscillator circuit 81 to the clock of the oscillator circuit 82, based on decision results from the monitor circuit 83. JP-A No. S61 (1986)-41243 discloses an apparatus for detecting abnormal clock pulses.
The present inventor has recognized that a clock with an abnormal waveform output from a PLL circuit may cause problems such as faulty operation in other function circuits. The problems still remain even if using technology as in JP-A No. H10 (1998)-124167 that selectively outputs the basic clock input to the PLL circuit or clock output from the PLL circuit.